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Final Electrical Specifications
LTC1096L/LTC1098L Low Voltage, Micropower Sampling 8-Bit Serial I/O A/D Converters
December 1995
FEATURES
s s s s s s s s
DESCRIPTIO
Specified at 2.65V Minimum Supply Maximum Supply Current: 80A Auto Shutdown to 1nA 8-Pin SO Package On-Chip Sample-and-Hold Conversion Time: 32s Sample Rates: 16.5ksps I/O Compatible with SPI, MICROWIRETM, etc.
APPLICATI
s s s s s
S
The LTC(R)1096L/LTC1098L are 3V micropower, 8-bit successive approximation sampling A/D converters. They typically draw only 40A of supply current when converting and automatically power down to a typical supply current of 1nA between conversions. They are packaged in 8-pin SO packages and operate on a 3V supply. These 8bit, switched capacitor, successive approximation ADCs include a sample-and-hold. The LTC1096L has a single differential analog input. The LTC1098L offers a software selectable 2-channel multiplexed input. On-chip serial ports allow efficient data transfer to a wide range of microprocessors and microcontrollers over three wires. This, coupled with micropower consumption, makes remote location possible and facilitates transmitting data through isolation barriers. The circuits can be used in ratiometric applications or with an external reference. The high impedance analog inputs and the ability to operate with reduced spans (to 1V full scale) allow direct connection to sensors and transducers in many applications, eliminating the need for gain stages.
, LTC and LT are registered trademarks of Linear Technology Corporation. MICROWIRE is a registered trademark of National Semiconductor Corporation.
Battery-Operated Systems Remote Data Acquisition Isolated Data Acquisition Battery Monitoring Temperature Measurement
TYPICAL APPLICATI
10W, SO-8 Package, 8-Bit A/D Converter Samples at 200Hz and Runs Off a 3V Battery
1F 3V
1000
SUPPLY CURRENT, ICC (A)
100
ANALOG INPUT 0V TO 3V RANGE
1 CS/ VCC SHDN 2 +IN CLK LTC1096L 3 -IN DOUT 4 GND VREF
8 7 6 5 SERIAL DATA LINK
MPU SERIAL DATA LINK (MICROWIRE AND SPI COMPATIBLE)
10
1096/8 TA01
1 0.1 1 10 SAMPLE FREQUENCY (kHz) 100
1096/8 TA02
Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
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Supply Current vs Sample Rate
UO
UO
1
LTC1096L/LTC1098L ABSOLUTE AXI U RATI GS U WW W
(Notes 1 and 2)
Supply Voltage (VCC) to GND ................................... 12V Voltage Analog and Reference ................ -0.3V to VCC + 0.3V Digital Inputs......................................... -0.3V to 12V Digital Outputs ........................... -0.3V to VCC + 0.3V Power Dissipation.............................................. 500mW
Operating Temperature LTC1096LAC/LTC1098LAC .................... 0C to 70C LTC1096LAI/LTC1098LAI .................. - 40C to 85C LTC1096LC/LTC1098LC......................... 0C to 70C LTC1096LI/LTC1098LI ....................... - 40C to 85C Storage Temperature Range ................. - 65c to 150C Lead Temperature (Soldering, 10 sec.)................ 300C
PACKAGE/ORDER I FOR ATIO
TOP VIEW CS/ 1 SHDN +IN 2 -IN 3 GND 4 8 VCC 7 CLK 6 DOUT 5 VREF
ORDER PART NUMBER LTC1096LACS8 LTC1096LAIS8 LTC1096LCS8 LTC1096LIS8 S8 PART MARKING 096LIA 1096LA 1096LI 1096L
TOP VIEW CS/ 1 SHDN CH0 2 CH1 3 GND 4 8 VCC(VREF) 7 CLK 6 DOUT 5 DIN S8 PACKAGE 8-LEAD PLASTIC SO
TJMAX = 150C, JA = 175C/W
S8 PACKAGE 8-LEAD PLASTIC SO
TJMAX = 150C, JA = 175C/W
Consult factory for Military grade parts.
RECO
SYMBOL VCC fCLK tCYC thDI tsuCS tWAKEUP
E DED OPERATI G CO DITIO S
CONDITIONS VCC = 2.65V LTC1096L, fCLK = 250kHz LTC1098L, fCLK = 250kHz VCC = 2.65V VCC = 2.65V, LTC1096L VCC = 2.65V, LTC1098L VCC = 2.65V, LTC1096L VCC = 2.65V, LTC1098L VCC = 2.65V VCC = 2.65V VCC = 2.65V VCC = 2.65V LTC1096L, fCLK = 250kHz LTC1098L, fCLK = 250kHz MIN 2.65 25 58 58 450 1 1 10 10 1 1.6 1.6 2 56 56 TYP MAX 4.0 250 UNITS V kHz s s ns s s s s s s s s s s
PARAMETER Supply Voltage Clock Frequency Total Cycle Time Hold Time, DIN After CLK Setup Time CS Before First CLK (See Operating Sequence) Wakeup Time CS Before First CLK After First CLK (See Figure 1, LTC1096L Operating Sequence) Wakeup Time CS Before MSBF Bit CLK (See Figure 2, LTC1098L Operating Sequence)
tsuDI tWHCLK tWLCLK tWHCS tWLCS
Setup Time, DIN Stable Before CLK CLK High Time CLK Low Time CS High Time Between Data Transfer Cycles CS Low Time During Data Transfer
2
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(Note 3)
ORDER PART NUMBER LTC1098LACS8 LTC1098LAIS8 LTC1098LCS8 LTC1098LIS8 S8 PART MARKING 098LIA 1098LA 1098LI 1098L
U WW
LTC1096L/LTC1098L
CO VERTER A D
PARAMETER Resolution (No Missing Code) Offset Error Linearity Error Full Scale Error Total Unadjusted Error (Note 5) Analog Input Range REF Input Range (Note 6) Analog Input Leakage Current
VCC = 2.65V, VREF = 2.5V, fCLK = 250kHz, unless otherwise noted.
CONDITIONS
q
DIGITAL A D DC ELECTRICAL CHARACTERISTICS
VCC = 2.65V, VREF = 2.5V, fCLK = 250kHz, unless otherwise noted.
SYMBOL VIH VIL IIH IIL VOH VOL IOZ ISOURCE ISINK IREF PARAMETER High Level Input Voltage Low Level Input Voltage High Level Input Current Low Level Input Current High Level Output Voltage Low Level Output Voltage Hi-Z Output Leakage Output Source Current Output Sink Current Reference Current CONDITIONS VCC = 3.6V VCC = 2.65V VIN = VCC VIN = 0V VCC = 2.65V, IO = 10A IO = 360A VCC = 2.65V, IO = 400A CS =High VOUT = 0V VOUT = VCC CS = VCC tCYC 200s, fCLK 50kHz tCYC = 58s, fCLK = 250kHz CS = VCC LTC1096L, LTC1098L, tCYC 200s, fCLK 50kHz tCYC = 58s, fCLK = 250kHz tCYC 200s, fCLK 50kHz tCYC = 58s, fCLK = 250kHz
q q q q q q q q q q q q q q q q
ICC
Supply Current
WU
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ULTIPLEXER CHARACTERISTICS
LTC1096LA/LTC1098LA MIN TYP MAX 8 0.5 0.5 0.5 1 - 0.05V to VCC + 0.05V - 0.05V to VCC + 0.05V
q q q q
LTC1096L/LTC1098L MIN TYP MAX 8 1 1 1 1.5
UNITS Bits LSB LSB LSB LSB V V
(Note 4)
VREF = 2.5V (Note 6) 2.65 VCC 4.0V (Note 7)
q
1
1
A
MIN 1.9
TYP
MAX 0.45 2.5 - 2.5
UNITS V V A A V V
2.4 2.1
2.64 2.50 0.3 3 - 10 15 0.001 2.5 3.500 7.5 35.00 50.0 0.001 40 120 44 155 3 80 180 88 230
V A mA mA A A A A A A A A
3
LTC1096L/LTC1098L AC CHARACTERISTICS
VCC = 2.65V, VREF = 2.5V, fCLK = 250kHz, unless otherwise noted.
SYMBOL tSMPL fSMPL(MAX) tCONV tdDO tdis ten thDO tf tr CIN PARAMETER Analog Input Sample Time Maximum Sampling Frequency Conversion Time Delay Time, CLK to DOUT Data Valid Delay Time, CS to DOUT Hi-Z Delay Time, CLK to DOUT Enable Time Output Data Remains Valid After CLK DOUT Fall Time DOUT Rise Time Input Capacitance See Operating Sequences See Test Circuits See Test Circuits See Test Circuits CLOAD = 100pF See Test Circuits See Test Circuits Analog Inputs Digital Input The q denotes specifications which apply over the full operating temperature range. Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Note 2: All voltage values are with respect to GND. Note 3: This device is specified at 2.65V. Consult factory for 5V specified devices. Note 4: Linearity error is specified between the actual end points of the A/D transfer curve. Note 5: Total unadjusted error includes offset, full scale, linearity, multiplexer and hold step errors. On Channel Off Channel
q q q q q
CONDITIONS See Operating Sequences
q
MIN 16.5
TYP 1.5 8 500 220 160 400 70 50 25 5 5
MAX
UNITS CLK Cycles kHz CLK Cycles
1000 800 480 250 200
ns ns ns ns ns ns pF pF pF
Note 6: Two on-chip diodes are tied to each reference and analog input which will conduct for reference or analog input voltages one diode drop below GND or one diode drop above VCC. This spec allows 50mV forward bias of either diode for 2.65V VCC 3.6V. This means that as long as the reference or analog input does not exceed the supply voltage by more than 50mV, the output code will be correct. To achieve an absolute 0V to 3V input voltage range will therefore require a minimum supply voltage of 2.950V over initial tolerance, temperature variations and loading. Note 7: Channel leakage current is measured after the channel selection.
PI FU CTIO S
LTC1096L
CS/SHDN (Pin 1): Chip Select Input. A logic low on this input enables the LTC1096L. A logic high on this input disables the LTC1096L and disconnects the power to the LTC1096L. IN+ (Pin 2): Analog Input. This input must be free of noise with respect to GND. IN- (Pin 3): Analog Input. This input must be free of noise with respect to GND. GND (Pin 4): Analog Ground. GND should be tied directly to an analog ground plane. VREF (Pin 5): Reference Input. The reference input defines the span of the A/D converter and must be kept free of noise with respect to GND. DOUT (Pin 6): Digital Data Output. The A/D conversion result is shifted out of this output. CLK (Pin 7): Shift Clock. This clock synchronizes the serial data transfer. VCC (Pin 8): Power Supply Voltage. This pin provides power to the A/D converter. It must be free of noise and ripple by bypassing directly to the analog ground plane.
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LTC1098L
CS/SHDN (Pin 1): Chip Select Input. A logic low on this input enables the LTC1098L. A logic high on this input disables the LTC1098L and disconnects the power to the LTC1098L. CHO (Pin 2): Analog Input. This input must be free of noise with respect to GND.
LTC1096L/LTC1098L
PI FU CTIO S
CH1 (Pin 3): Analog Input. This input must be free of noise with respect to GND. GND (Pin 4): Analog Ground. GND should be tied directly to an analog ground plane. DIN (Pin 5): Digital Data Input. The multiplexer address is shifted into this pin. DOUT (Pin 6): Digital Data Output. The A/D conversion result is shifted out of this output. CLK (Pin 7): Shift Clock. This clock synchronizes the serial data transfer. VCC (VREF) (Pin 8): Power Supply Voltage. This pin provides power and defines the span of the A/D converter. It must be free of noise and ripple by bypassing directly to the analog ground plane
TEST CIRCUITS
Load Circuit for tdDO, tr and tf
1.4V
VOH VOL tr
LTC1096/98 * TC01
DOUT 100pF
Load Circuit for tdis and ten
CS
TEST POINT
DOUT WAVEFORM 1 (SEE NOTE 1) tdis DOUT WAVEFORM 2 (SEE NOTE 2) 10%
DOUT 100pF tdis WAVEFORM 1
LTC1096/98 * TC03
U
3k
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Voltage Waveforms for DOUT Rise and Fall Times, tr, tf
3k TEST POINT
DOUT
tf
LTC1096/98 * TC02
Voltage Waveforms for tdis
VIH
VCC tdis WAVEFORM 2, t en
90%
NOTE 1: WAVEFORM 1 IS FOR AN OUTPUT WITH INTERNAL CONDITIONS SUCH THAT THE OUTPUT IS HIGH UNLESS DISABLED BY THE OUTPUT CONTROL. NOTE 2: WAVEFORM 2 IS FOR AN OUTPUT WITH INTERNAL CONDITIONS SUCH THAT THE OUTPUT IS LOW UNLESS DISABLED BY THE OUTPUT CONTROL.
LTC1096/98 * TC04
Voltage Waveforms for DOUT Delay Time, tdDO
CLK VIL tdDO VOH DOUT VOL
LTC1096/98 * TC05
5
LTC1096L/LTC1098L TEST CIRCUITS
Voltage Waveforms for ten
LTC1096L CS t WAKEUP CLK 1
DOUT t en
B7 VOL
LTC1096/98 * TC06
LTC1098L CS
DIN
START
CLK
1
2
3
4
5
DOUT t en
B7 VOL
LTC1096/98 * TC07
APPLICATI
S I FOR ATIO
INPUT DATA WORD The LTC1096L requires no DIN word. It is permanently configured to have a single differential input. The conversion result, in which the output on the DOUT line is presented in MSB-first sequence followed by LSB sequence, provides easy interface to MSB- or LSB-first serial ports. The LTC1098L latches data into the DIN input on the rising edge of the clock. The input data words are defined as follows:
SGL/ START DIFF ODD/ MSBF SIGN
MUX MSB-FIRST/ ADDRESS LSB-FIRST
LTC1096/9 * AI01
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Start Bit The first "logical one" clocked into the DIN input after CS goes low is the start bit. The start bit initiates the data transfer. The LTC1098L will ignore all leading zeroes which precede this logical one. After the start bit is received, the remaining bits of the input word will be clocked in. Further inputs on the DIN pin are then ignored until the next CS cycle. Multiplexer (MUX) Address The bits of the input word following the START bit assign the MUX configuration for the requested conversion. For a given channel selection, the converter will measure the voltage between the two channels indicated by the "+" and "-" signs in the selected row of the following tables. In
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LTC1096L/LTC1098L
APPLICATI S I FOR ATIO U
not use wire wrapping techniques to breadboard and evaluate the device. To achieve the optimum performance use a printed circuit board. The GND pin (Pin 4) should be tied directly to the ground plane with minimum lead length. Bypassing For good performance, the LTC1096L/LTC1098L VCC and VREF pins must be free of noise and ripple. Any changes in the VCC and VREF voltage with respect to ground during the conversion cycle can induce errors or noise in the output code. Bypass the VCC and VREF pins directly to the analog ground plane with a minimum 0.1F capacitor and with leads as short as possible. The LTC1098L combines VCC and VREF into one pin, VCC(VREF), which can be bypassed by a 0.1F capacitor. Analog Inputs Because of the capacitive redistribution A/D conversion techniques used, the analog inputs of the LTC1096L/ LTC1098L have capacitive switching input current spikes. These current spikes settle quickly and do not cause a problem. But if large source resistances are used or if slow settling op amps drive the inputs, take care to ensure the transients caused by the current spikes settle completely before the conversion begins.
t CYC CS POWER DOWN CLK tsuCS tWAKEUP DOUT Hi-Z NULL BIT B4 B3 B2 B1 B0 B1 B2 B3 B4 B5 B6 B7 Hi-Z FILLED WITH ZEROES
LTC1096/98 F01
single-ended mode, all input channels are measured with respect to GND.
LTC1098L Channel Selection
MUX ADDRESS CHANNEL # ODD/SIGN CH0 SGL/DIFF CH1 GND 0 1 - + 1 1 - + 0 0 - + 1 0 + -
LTC1096/8 * AI02
MSB-First/LSB-First (MSBF) The output data of the LTC1098L is programmed for MSB-first or LSB-first sequence using the MSBF bit. When the MSBF bit is a logical one, data will appear on the DOUT line in MSB-first format. Logical zeroes will be filled in indefinitely following the last data bit. When the MSBF bit is a logical zero, LSB-first data will follow the normal MSB-first data on the DOUT line (see Figures 1 and 2). ANALOG CONSIDERATIONS Grounding The LTC1096L/LTC1098L should be used with an analog ground plane and single point grounding techniques. Do
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B7
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B6
B5 tCONV
Figure 1. LTC1096L Operating Sequence
7
LTC1096L/LTC1098L
APPLICATI
S I FOR ATIO
MSB-FIRST DATA (MSBF = 0)
tCYC
CS tWAKEUP CLK tsuCS START DIN SGL/ DIFF DOUT Hi-Z tSMPL MSBF NULL BIT B7 B6 B5 tCONV B4 B3 B2 B1 B0 B1 B2 B3 B4 B5 B6 B7 ODD/ SIGN DON'T CARE
Figure 2. LTC1098L Operating Sequence Example: Differential Inputs (CH+, CH-)
PACKAGE DESCRIPTION
Dimensions in inches (millimeters) unless otherwise noted.
S8 Package 8-Lead Plastic Small Outline (Narrow 0.150)
(LTC DWG # 05-08-1610)
0.189 - 0.197* (4.801 - 5.004) 8 7 6 5
0.010 - 0.020 x 45 (0.254 - 0.508) 0.008 - 0.010 (0.203 - 0.254)
0.053 - 0.069 (1.346 - 1.752) 0- 8 TYP
0.016 - 0.050 0.406 - 1.270
0.014 - 0.019 (0.355 - 0.483)
*DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE **DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
RELATED PARTS
PART NUMBER DESCRIPTION COMMENTS Low Power, Small Size, Low Cost Low Power, Small Size, Low Cost 12-Bit ADC in SO-8 8-Channel 12-Bit Serial I/O 4-Channel 12-Bit Serial I/O, Micropower LTC1096/LTC1098 8-Pin SO, Micropower 8-Bit ADC LTC1196/LTC1198 8-Pin SO, 1Msps 8-Bit ADC LTC1285/LTC1288 8-Pin SO, 3V Micropower 12-Bit ADC LTC1289 LTC1584L Multiplexed 3V 12-Bit ADC Multiplexed 3V 12-Bit ADC
8
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 q FAX: (408) 434-0507 q TELEX: 499-3977
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POWER DOWN Hi-Z FILLED WITH ZEROES
LTC1096/98 F02
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0.004 - 0.010 (0.101 - 0.254)
0.228 - 0.244 (5.791 - 6.197)
0.150 - 0.157** (3.810 - 3.988)
0.050 (1.270) BSC
1
2
3
4
SO8 0695
LT/GP 1295 5K REV A * PRINTED IN USA
(c) LINEAR TECHNOLOGY CORPORATION 1995

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